MDSL Framer/Mapper for 64 ~ 784 kbps Applications

General Description

The CIC92310 is a complete MDSL framer/mapper that multiplexes and demultiplexes framed or unframed 2.048 Mbps E1 data stream onto the MDSL lines.

CIC92310 Block Diagram

The CIC92310 interfaces directly with the Level One SK70720/SK70721 MDSL data pump and industry standard E1 Framers or Line Interface ICs for E1 application. The CIC92310 also interfaces directly with the CODEC IC for pairgain application. The framer will also provide the V.35/EIA530/G.703 interface in next version. The framer/mapper is controlled and monitored by an external processor using an 8-bit Intel or Motorola compatible parallel interface. The framer/mapper provides both general interrupts and MDSL frame pulse interrupts synchronized to the MDSL frame rate.

The CIC92310 also provides interval programmable Z-bit interrupts for voice signaling utilization. The CIC92310 provides fully programmable mapping between the 2.048MHz PCM bus and MDSL interfaces. The CIC92310 provides support for system performance monitoring with internal CRC, FEBE and BPV error counters and the capability to inject these errors.

The framer/mapper automatically controls the synchronization between the MDSL loop timing and the payload timing using a digital PLL for E1 timing recovery and a transmitter stuffing control circuit. The CIC92310 provide both synchronous and plesiochronous timing mode for different applications. In order to reduce the waiting time jitter in plesiochronous system, an advanced waiting time jitter reduction algorithm is implemented to guarantee the output jitter/wander performance.

Features

Reference with ETSI ETR-152 requirements
Interfaces with Level One MDSL Data Pumps and industry standard E1 Framers/Line Interface ICs
8-bit, Intel or Motorola compatible parallel processor interface with programmable and MDSL frame pulse interrupts
Interval programmable Z-bit interrupts
E1 to MDSL Loop Mux/Demultiplexing
- Programmable timeslot mapping

Accepts framed or unframed E1 data
IDLE Code Insertion provides channel blocking in mux and demux directions - DS0 Channel Grouping

Loopbacks toward E1 and MDSL interfaces
Diagnostics/Performance monitoring
QRSS Pattern Generation and Detection
CRC, BPV and FEBE counters and error generators
User definable overhead channel
MDSL Overhead Management
DPLL for 2.048 MHz Timing Recovery
MDSL Transmit Stuffing Contro

Name:	Lily Chiang-Lin IC Product Marketing Dept., B300
Tel:	+886-3-5917919
Fax:	+886-3-5820099
E-mail:	lily@ccl.itri.org.tw
Address:	ITRI Bldg 14, 195-11, Sec 4, Chung Hsing Rd. Chutung, Hsinchu, Taiwan, R.O.C.