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Fractional E1 Data Service unit

General Description

CIC92520 is a fractional E1 data service unit (FE1 DSU) which is able to map framed or unframed 2.048Mbps / 4.096Mbps / 8.192Mbps / 16.384Mbps E1 data stream to/from two independent Nx64k DTE (Digital Terminal Equipment) channel signals without restriction on binary content. CIC92520 interfaces directly with DTE channel driver ICs and E1 digital line facilities. This FE1 DSU supports three DTE ports, including two Nx64k data channels and one FE1 DTE channel. The two Nx64k data ports provide the V.35/EIA530/G.703 data channel interface option according field requirement. The FE1 port provides fractional E1 data interface for E1 time slot added/dropped function. CIC92520 also interfaces directly with the codec ICs for pair-gain applications. 16 programming I/O pins are provided for status management in accordance with Nx64k DTE data interface. CIC92520 supports several user-defined timing sources for specific field applications without external glue logic. The built-in digital clock synthesizers can automatically make the synchronization between the Nx64k DTE channel timing, FE1 DTE channel timing and the E1 line timing. The DSU is controlled and monitored by an external processor using an 8-bit Intel/Motorola compatible parallel interface.

Functional Block Diagram

Features

  • Provide two DTE Nx64K(N=1~32) data ports, 64K~2048Kbps data rate supported with user arranged 64Kbps channel time slot assignment
  • Provide one Fractional E1(FE1) DTE channel port for E1 time slot added / dropped function, 2.048Mbps/4.096Mbps date rate supported
  • Provide 12-line codec frame pulse output for pair-gain application
  • 16.384M/8.192M/4.096M/2.048Mbps E1 PCM digital line rate supported, providing up to 8 DTE data ports interface with 4 CIC92520 parallel cascaded
  • V.35/EIA530/G.703 DTE channel inter-face supported
  • Provide 16 user-defined I/O pins for status management of the two N¡Ñ64K DTE channels.
  • No external VCO required, only one OSC(Oscillator) is needed for built-in all-digital Nx64K (N=1~32) clock synthesizer and 2.048MHz / 4.096MHz clock synthesizer
  • User selectable timing source for specific applications ¡V (1) E1 or FE1 loop timing source (2) DTE data port-1 or port-2 timing source (3) internal (free-run) timing source (4) external timing source
    • Eight-bit, Intel / Motorola compatible parallel processor interface with Programmable timeslot mapping in FE1, Codec, and data port1/port2 interfaces when interfaced 2.048M/4.096Mbps E1/PCM line rate
    • 64x64Kbps(4096Kbps)-base timeslot mapping in data port1/port2 interfaces when interfaced 8.192M/16.384Mbps PCM line rate
    • E1/FE1 frame pulse output capability in DTE, internal and external timing mode
    • Fault diagnosis with loopback test toward E1, FE1, DTE and codec channel interfaces
    • Data and clock polarity selection in E1, FE1 and data port1/port2 interfaces
    • 2143/2181 mode supported in E1/FE1 interface - Auto-detect timeslot number in FE1 and data port 1/port 2 timeslot mapping table
    • User defined E1/FE1/Codec channel idle code
    • AIS insertion in data port 1/port 2 channel
    • Programmable long/short and delay mode codec frame pulse output
    • Internal buffer read/write collision monitoring bits
  • Single +5V power supply operation.